The present invention relates to semiconductor devices, and more particularly, to a standard cell used in a semiconductor device.
System level designers often integrate different logic functions into an integrated circuit (IC) using commercially available design tools including electronic design automation (EDA) and computer aided design (CAD) tools. Examples of ICs include microprocessors, microcontroller units (MCUs), systems-on-chips (SoCs), and application specific integrated circuits (ASICs). The logic functions are realized in the IC using standard cell methodology. A standard cell includes a plurality of transistors, viz., complementary metal-oxide semiconductor (CMOS) devices that are used to implement logic functions. The logic functions may include Boolean functions (e.g., AND, OR, and NOT), storage functions (e.g., flip-flops, latches, and buffers), and digital combinational functions (e.g., multiplexers and demultiplexers).
Each standard cell has a predetermined geometry (width and height). The EDA and CAD design tools include a library (known as a standard cell library) that stores the standard cell definitions for these logic functions. During semiconductor device design, the design tool selects one or more standard cells from the cell library based on the logic design and the process parameters (i.e., size and width of the standard cell) and places the cells in rows and columns. Upon completing the placement, the semiconductor device design is simulated, verified, and subsequently transferred to a chip (i.e., formed in Silicon).
FIGS. 1A-1C are schematic layout diagrams of first through third conventional standard cells 102a-102c (collectively referred to as standard cells 102). The first standard cell 102a may be a logic AND function, the second standard cell 102b a logic OR function, and the third standard cell 102c a logic NOT function.
The first standard cell 102a includes first and second active regions 104a and 104b (collectively referred to as active regions 104) formed over a substrate (not shown). A gate (poly) electrode strip 106a is disposed over the first and second active regions 104a and 104b. The gate electrode strip 106a forms a first MOS device with the first active region 104a and a second MOS device with the second active region 104b. As understood by those of skill in the art, within a standard cell 102, each gate electrode 106 forms a p-type MOS (PMOS) device with one active region 104 and a n-type MOS (NMOS) device with opposing active region 104.
Similarly, the second standard cell 102b includes third and fourth active regions 104c and 104d formed over the substrate and gate electrode strips 106b and 106c disposed over the third and fourth active regions 104c and 104d to form third and fourth MOS devices. The third standard cell 102c also has fifth and sixth active regions 104e and 104f formed over the substrate and gate electrode strips 106d, 106e, and 106f disposed over the fifth and sixth active regions 104e and 104f to form fifth and sixth MOS devices.
Each standard cell 102 has a boundary that extends at a predetermined distance along its outer periphery. The boundary includes first, second, third and fourth boundaries. The first and second boundaries lie at opposite ends of the standard cell 102. The third and fourth boundaries also lie at opposite ends of the standard cell 102. As can be seen, the first through fourth boundaries are akin to the sides of a rectangle. The first active region 104a is at a distance (a) from the first boundary and the second active region 104b is at a distance (a′) from the second boundary. The first and second active regions 104a and 104b are at a distance (b) from the third boundary and at a distance (b′) from the fourth boundary. The third active region 104c is at a distance (c) from the first boundary and the fourth active region 104d is at a distance (c′) from the second boundary. The third and fourth active regions 104c and 104d are at a distance (d) from the third boundary and at a distance (d′) from the fourth boundary. The fifth active region 104e is at a distance (e) from the first boundary and the sixth active region 104f is at a distance (e′) from the second boundary. The fifth and sixth active regions 104e and 104f are at a distance (f) from the third boundary and at a distance (f′) from the fourth boundary.
The region between the gate electrodes 106 and corresponding active regions 104 is filled with a shallow trench isolation (STI) region. When the MOS devices are formed close to each other, the amount of STI required is less and vice-versa. Since the STI introduces compressive stresses, a wider STI increases the performance of a PMOS device and degrades the performance of an NMOS device, while a narrow STI exhibits exactly the opposite effects.
During device design, the design tools place the standard cells 102 in rows and columns to realize the respective logic functions. For example, as shown in FIG. 2A, the first and second standard cells 102a and 102b are abutted horizontally, i.e., the fourth boundary of the first standard cell 102a overlaps with the third boundary of the second standard cell 102b. The distance (b′) of the first and second active regions 104a and 104b from the overlapping boundary differs substantially from the distance (d) of the third and fourth active regions 104c and 104d from the overlapping boundary. This difference affects the impact of stresses offered by the varying width of STI, which deteriorates the carrier mobility and saturation current and introduces delay and leakage, thereby degrading the overall performance of the MOS devices. The problem persists when the first and second standard cells 102a and 102b are abutted vertically, i.e., when the second boundary of the first standard cell 102a overlaps with the first boundary of the second standard cell 102b, as shown in FIG. 2B. To avoid the impact of stresses due to vertical abutting, a dummy diffusion layer 108 is formed over the overlapping boundary (as shown in FIG. 2B). However, the dummy diffusion layer 108 increases the area overhead of the standard cell as well as the IC.
In light of the foregoing, there is a need for a standard cell design that reduces variation in stress caused by varying width of STI, that improves carrier mobility and saturation current, reduces delay and leakage, improves overall performance of the standard cell, and that overcomes the above-mentioned limitations of existing standard cells.